Such a synchronizing circuit is already known in the art from the article "A 660 Mbit/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission", by M. Banu et al., ISSCC '93, digest of technical papers, pp. 102-103, IEEE.
In this known synchronizing device the clock phase adjustment means comprises two voltage controlled oscillators alternately started and stopped by the level transitions in the input data, as shown in FIG. 1 of the article. In this way the output signals of the oscillators constitute phase shifted versions of the local clock signal, called "External Reference Frequency". This frequency is accurately reproduced in these output signals thanks to the depicted mechanism involving the use of a phase locked loop and a third voltage controlled oscillator matched to the previous two. The OR'ing of the above outputs then verifiably leads to the data clock signal having a correct phase, i.e. having level transitions aligned to those of the input data.
As argued in the article, in high-speed burst-mode applications commonly associated to the emergence of ATM or Asynchronous Transfer Mode technology, such an open-loop approach for recovering the data clock signal is preferable over conventional closed loop circuits, such as phase locked loops, since the latter are characterized by a locking delay and require a high input data level transition density to remain in the locked condition. By using the above open-loop strategy these problems are avoided as recovery of the data clock phase is performed instantaneously at the occurrence of an input data level transition, while the accuracy of the ratio of the local clock signal and input data frequencies ensures that a loss of phase synchronism before occurrence of a new input data level transition is highly unlikely.
However, the known implementation of this open-loop approach has a number of drawbacks particularly with respect to integrated circuit or IC technology. Indeed, the described circuit requires three matched voltage controlled oscillators since otherwise the above accuracy of the generated frequency is not guaranteed. Also, the known synchronizing circuit uses a phase locked loop at very high operating frequencies which is unattractive for stability reasons. But most importantly does the known circuit require a local clock signal having a frequency equal to that of the input data. Indeed, it is very difficult to generate such a local clock frequency accurately and furthermore such a high frequency complicates the circuit since all building blocks need to operate at this frequency.